A semiconductor memory IC, such as a DRAM, includes an array of memory cells organized into rows and columns. Bit lines are provided for each column of memory cells, and each memory cell is connected to the bit lines corresponding to the column in which the memory cell is located. Likewise, word lines are provided for each row of memory cells, and each memory cell is connected to the word line corresponding to the row in which the memory cell is located.
FIG. 1 shows a portion of a conventional DRAM 10. A single memory cell is shown formed from a MOSFET 22 having its source connected to a capacitor 24. The gate of the MOSFET 22 is connected to a word line (WL) 42 of the row in which the cell 20 is located and the drain of the MOSFET is connected to a bit line (BL) 32 of the column in which the cell 20 is located. Also provided for the column in which the cell is located is a complementary bit line (BL') 24. A row decoder 44 is connected to the word line 42.
Also connected to the word line 42 and bit lines 32, 34 is a precharge circuit 50. The precharge circuit 50 includes an inverter 51 receiving a signal EQ at its input. The output of the inverter 51 is connected to the word line 42. Also provided is a voltage source 53 having a voltage level of V.sub.DD /2 where V.sub.DD is the voltage level of the high voltage power supply bus. Connected to the voltage source 53 is a current limiting current source 55 formed as an NMOSFET 55 with a long channel length L. The current outputted by the current source 55 is provided to the sources of switch NMOSFETs 56 and 57. Each switch NMOSFET 56 and 57 receives the signal EQ at its gate. The drain of NMOSFET 56 is connected to the bit line 32 and the drain of NMOSFET 57 is connected to the complementary line 34. Connected across the pair of bit lines 32, 34 is an equalizing NMOSFET 58. The gate of NMOSFET 58 also receives the signal EQ.
The operation of the DRAM 10 has two modes, namely, a standby mode, and an access mode. During the standby mode, no cells of the memory array are accessed. Rather, the DRAM 10 places the bit line pair 32, 34, and the word lines, e.g., word line 42, into a state that enables quick access the access mode is initiated. To that end, the signal EQ is set to the high voltage level V.sub.DD. This causes the inverter 51 to drive the word lines, including word line 42, to the low voltage level V.sub.SS of the low voltage power supply bus. Meanwhile, MOSFETs 56 and 57 turn on. "Long L" current driver 55, which is permanently turned on by virtue of having its gate connected to the high voltage power supply bus, drives the bit line pairs to which it is connected, including bit line pair 32, 34, to the standby voltage level of one half of the high voltage level, i.e., the voltage level V.sub.DD /2 of the voltage source 53 connected thereto. NMOSFET 58 attempts to evenly distribute the supplied current across the bit line 32 and the complement bit line 34 so that they charge to approximately the same level.
During the access mode, the signal EQ is set to the low voltage level V.sub.SS. Inverter 51 is only enabled when the signal E is the high voltage level V.sub.DD and therefore does not drive the word line 42 to any voltage level. A unique address of the cell 20 is externally supplied which is divided into a row address, indicating the word line connected to the cell 20, and a column address, indicating the bit line pair connected to the cell 20. The row decoder 44 receives the row address and activates the appropriate word line, e.g., the word line 42, indicated by the row address. Likewise, a column decoder (not shown) activates the bit line pair, e.g., the bit line pair 32, 34, indicated by the column address. In the case of a read operation, this is achieved by driving the activated word line 42 to the high voltage level V.sub.DD and monitoring the differential voltage outputted on the activated bit line pair 32, 34. During the read operation, the cell 20 changes the voltage of the bit line 32 in a particular way relative to a charge stored on its capacitor 24 (if any). If the voltage of the bit line 32 drops, a logic `0` is detected. If the voltage on the bit line 32 increases, a logic `1` is detected. A sense amplifier (not shown) connected to the bit line pair 32, 34 amplifies the differential voltage of the bit line pair 32, 34 and outputs this differential voltage as the logic value read from the cell 20. During a write operation, a sense amplifier changes the relative voltages of the bit line pair 32, 34 so as to store a particular charge on the capacitor 24 that may be read out later.
DRAMs are fabricated in batches. Typically, a certain number of the fabricated DRAMs are defective. Defects most commonly occur in the memory array, where the geometrical features of the word lines 42, bit line pairs 32,34, and cell components 22 and 24 are minimized to increase the 20 storage capacity of the DRAM 10. Often, a DRAM 10 is provided with redundant "repair" rows and or columns of cells. The redundant rows and/or columns of cells have their own word lines and bit line pairs. A redundant row or column may be substituted for a defective row or column by testing the DRAM to identify a defective row or column and blowing one or more fuses for causing the DRAM row or column decoder to access the redundant row or column in place of the defective row or column, when an attempt is made to access a cell in the defective row or column.
In an attempt to conserve IC layout space, the DRAM 10 is provided with fewer precharge circuits 50 than word lines or column lines. For example, as shown in FIG. 2, in a 64 Mbit DRAM, 64 blocks of memory cell may be provided, wherein each block has 1,024 pairs of bit lines 32, 34. One precharge circuit 50 may be provided for each block which precharges 1,024 bit line pairs 32, 34. Referring again to FIG. 1, assume that there is a defect in the particular pair of bit lines 32, 34, namely, a short circuit 60 from the bit line 32 to the word line 42. This pair of bit lines 32, 34 will be replaced by a redundant repair column. Nevertheless, the defective bit line pair 32, 34 is still driven by the same precharge circuit 50 during standby mode.
Such a short circuit 60 can alone draw a current in excess of 75 .mu.A from the source 53. This is because the source 53 is attempting to drive the bit line 32 to the voltage V.sub.DD /2 while the short circuit 60 provides a conduction path to the word line 42 which the inverter 51 has driven to the low voltage level of V.sub.SS. Approximately 50 .mu.A may be needed during standby mode to drive the bit line pairs of the memory array assuming no short circuits. A low power specification exists for DRAMs used in portable devices such as laptop computers, cellular phones, etc. which specifies that no more than about 150-200 .mu.A can be drawn by a low power DRAM during standby mode. Therefore, if the DRAM 10 has two snort circuits 60, the total power consumption of the DRAM 10 may cause the DRAM 10 to fail the current consumption requirement of the low power specification.
To remedy this problem, conventional DRAM architectures 10 utilize a "long L" current source 55. As noted above, the long L current source 55 is so called because it has a long channel length. This causes the current source 55 to be resistive and to function as a current limiting current source. With the channel of the long L current source 55 set to a sufficient length, the current draw of the short circuit 60 can be limited to no more than 75 .mu.A. Thus, the DRAM 10 can have two short circuits and still remain within the standby current consumption requirements of the low power specification.
The use of a long NMOSFET 55 is not without penalty. A long L NMOSFET 55 takes a longer time to charge up each bit line pair to which it is connected to V.sub.DD /2. Recall, this is a necessary step prior to accessing the cells. In fact, the selection of channel length L of the NMOSFET 55 to limit short circuit current draw to 75 .mu.A is made as a tradeoff between limiting the short circuit current draw and minimizing the standby mode time. In addition, extra space is occupied by the larger NMOSFET 55 in the DRAM IC layout.
It is an object of the present invention to overcome the disadvantages of the prior art.
It is also an object of the present invention to improve the yield of DRAMs.